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Periodic Merges (24h) / merge-base(master,staging) → haskell-updates (push) Failing after 11m54s
Periodic Merges (6h) / staging-next → staging (push) Failing after 12m13s
Periodic Merges (24h) / staging-next-25.05 → staging-25.05 (push) Failing after 13m24s
Periodic Merges (24h) / release-25.05 → staging-next-25.05 (push) Failing after 14m28s
8 lines
125 B
Verilog
8 lines
125 B
Verilog
module helloworld (
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input wire[7:0] a,
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input wire[7:0] b,
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output wire[7:0] c,
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);
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assign c = a + b;
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endmodule
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